Phase locked loop (PLL) circuits are important parts of many wireless communication systems. A PLL circuit can be implemented as an analog PLL or a digital PLL. An analog PLL may include among other components a phase detector (PD), a charge pump (CP), an analog loop filter and a voltage controlled oscillator (VCO). In a digital PLL, the PD and/or CP and the analog loop filter may be respectively replaced with a time-to-digital converter (TDC) and a digital loop filter. A digital PLL may further include a crystal oscillator and may use a sigma-delta modulator along with a frequency divider in a negative feedback path. Spurs can show up at PLL output due to the on-chip coupling to a reference path including the crystal oscillator, the feedback path, or the VCO.
The chip, for example, a system-on-chip (SoC) may include multiple clocks running at the same time to generate multiple clock signals with different clock frequencies. A clock frequency of any of the clock signals and respective harmonics of the clock signals may intermodulate with, for example, a frequency of the crystal oscillator and/or the VCO to generate spurs. The spurs can adversely affect system performance, in particular, when the intermodulated frequencies are falling within a signal band of interest. For example, the spurs may degrade a constellation error, expressed as an error vector magnitude (EVM), of one or more receivers and transmitters implemented on the same chip.